Abstract

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.

Document Type

Patent

Status

Issued

Issue Date

1-29-1991

Patent Number

US 4989063 A [ 4,989,063 ]

CPC Classification

H 01 L 24/29

Application number

07/549672

Assignees

The United States of America as represented by the Secretary of the Air Force

Filing Date

4-24-1990

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