Abstract

A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to a raster scan image of the extracted and annotated electrical property values superimposed at their corresponding physical locations onto a physical layout image of the integrated circuit, preferably color-coded to further spotlight potential defects. The visual images are compared to as specified layout design parameters and to as manufactured parameters.

Document Type

Patent

Status

Issued

Issue Date

1-5-2016

Patent Number

US 9230050 B1 [9,230,050]

CPC Classification

G06F17/5072

Application number

14/484941

Assignees

Government of the United States, as represented by the Secretary of the Air Force, Wright-Patterson AFB, OH (US)

Filing Date

9-12-2014

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