Abstract

An active attestation apparatus verifies at runtime the integrity of untrusted machine code of an embedded system residing in a memory device while it is being run/used with while slowing the processing time less than other methods. The apparatus uses an integrated circuit chip containing a microcontroller and a reprogrammable logic device, such as a field programmable gate array (FPGA), to implement software attestation at runtime and in less time than is typically possible with comparable attestation approaches, while not requiring any halt of the processor in the microcontroller. The reprogrammable logic device includes functionality to load an encrypted version of its configuration and operating code, perform a checksum computation, and communicate with a verifier. The checksum algorithm is preferably time optimized to execute computations in the reprogrammable logic device in the minimum possible time.

Document Type

Patent

Status

Issued

Issue Date

8-21-2021

Patent Number

US 11086997 [ 11,086,997 ] ; US11086997B1

CPC Classification

H 04 L 9/088

Application number

16/248024

Assignees

United States of America as represented by the Secretary of the Air Force, Wright-Patterson AFB

Filing Date

1-15-2019

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