Date of Award

3-2023

Document Type

Thesis

Degree Name

Master of Science

Department

Department of Electrical and Computer Engineering

First Advisor

Richard Dill, PhD

Abstract

This document is a compilation of two scholarly articles that together compose a graduate thesis. The first article assesses the viability of commercially available JTAG debuggers to access runtime memory and register data, finding that commercial JTAG debuggers are not suitable for runtime data extraction for anomaly detection in cyber-physical systems due to slow memory and register access times. Because of this gap in technology, the second article designs, implements, and tests a novel, custom-built architecture named JTAG Data Extraction Tool (J-DET) for program counter-sampling. J-DET is the first device purpose-built to extract processor information in runtime for attack detection; it proves that high-speed, low-performance impact data extraction is possible via JTAG with purpose-built hardware. The J-DET architecture paves the way for future research into analysis methods for anomaly detection with program counter data, and modifications to the J-DET architecture to collect other hardware performance counter data for anomaly detection.

AFIT Designator

AFIT-ENG-MS-23-M-052

Comments

A 12-month embargo was observed for posting this thesis.

Approved for public release, case number on file.

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