Hardware-Verification Through Logic Extraction

Author

Michael A. Dukes

Date of Award

3-1992

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Department of Electrical and Computer Engineering

First Advisor

Frank M. Brown, PhD

Second Advisor

Joanne E. DeGroat, PhD [The Ohio State University]

Abstract

A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI designs up to 250,000 transistors in size. The properties of correctness, completeness, and guaranteed termination are examined for the extraction process.

AFIT Designator

AFIT-DS-ENG-92-1

DTIC Accession Number

ADA248087

Comments

The author's Vita page is omitted.

Recommended Citation

Dukes, Michael A., "Hardware-Verification Through Logic Extraction" (1992). Theses and Dissertations. 7357.
https://scholar.afit.edu/etd/7357