Date of Award

12-1992

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering

Department

Department of Electrical and Computer Engineering

First Advisor

Kim Kanzaki, PhD

Abstract

The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The other translation program converted the output of GENTEX into a schematic in EDIF. The results of the performance analysis showed that an extraction algorithm based on searching the data structures by node rather than by component type provided the best performance. The results also showed that comparing the number of connections to a node within a template to the actual number of connections to a node within the circuit being extracted, not only eliminated any connectivity problems but also increased performance.

AFIT Designator

AFIT-GE-ENG-92D-25

DTIC Accession Number

ADA259078

Comments

The author's Vita page is omitted.

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