Date of Award
12-1992
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering
Department
Department of Electrical and Computer Engineering
First Advisor
Mark Mehalic, PhD
Second Advisor
Joseph Sachinni, PhD
Abstract
The purpose of this thesis is to investigate two types of tracking loops used in Global Positioning System (GPS) receiver design. The first loop, the Delay Lock Loop (DLL), is a code tracking loop used to synchronize a locally generated pseudo-noise (PN) sequence with the PN sequence in the GPS satellite broadcast. Synchronization of the PN sequences is essential for de-spreading the direct-sequence spread spectrum (DS/SS) broadcast and demodulating the transmitted data. The second loop, the Modified Tanlock Loop (MTLL), is a carrier tracking loop used to synchronize the phase of a voltage controlled oscillator (VCO) with the carrier of the GPS satellite broadcast. Carrier synchronization is essential for optimum data demodulation. This thesis derives equations predicting the theoretical performance of each loops' ability to track a GPS signal corrupted by noise and signal dynamics arising from transmitter and/or receiver motion. In addition, computer simulations of the DLL and MTLL were developed and the results are presented. The simulations display phenomena which were not present in the theoretical predictions.
AFIT Designator
AFIT-GE-ENG-92D-20
DTIC Accession Number
ADA259315
Recommended Citation
Hird, James A., "Analysis and Simulation of Modified Tanlock and Delay Lock Loops for GPS Receiver Design" (1992). Theses and Dissertations. 7134.
https://scholar.afit.edu/etd/7134
Comments
The author's Vita page is omitted.