Date of Award

12-1992

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering

Department

Department of Electrical and Computer Engineering

First Advisor

Thomas C. Hartrum, PhD

Abstract

Many VLSI circuit designs are too large to be simulated with VHDL in a reasonable amount of time. One approach to reducing the simulation time is to distribute the simulation over several processors. This research creates an environment for designing and simulating structural VHDL circuits on the Intel iPSC/2 and iPSC/860 Hypercubes. Logic gates and system behaviors are partitioned among the processors, and signed changes are shared via event messages. Circuit simulations are run over the SPECTRUM parallel simulation testbed, and the null- message paradigm is used to avoid deadlock. Structural circuits ranging from forty to over one thousand logic gates are correctly simulated. Although no attempt is made to find optimal partitioning strategies, speedups are obtained for some configurations.

AFIT Designator

AFIT-GCS-ENG-92D-01

DTIC Accession Number

ADA258999

Comments

The author's Vita page is omitted.

Download

Share

COinS