Date of Award

12-1993

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering

Department

Department of Electrical and Computer Engineering

First Advisor

Mark Mehalic, PhD

Second Advisor

Joseph J. Sacchini, PhD

Third Advisor

Robert N. Riggins, PhD

Abstract

The purpose of this thesis was to investigate the performance of two types of tracking loops used in Global Positioning System (GPS) receivers. The first loop, the Delay-Lock Loop (DLL), is responsible for maintaining synchronization with the received PN sequence. The second loop, the Modified Tanlock Loop (MTLL), is responsible for maintaining synchronization with the carrier signal. The performance of the two loops is investigated first separately then their performance is evaluated when operated together. This thesis is an investigation on the ability of these two loops to overcome corruption of the input signal due to noise. Expanding the dynamic operating range of these loops can significantly improve GPS receiver operation. Results indicate the performance of the loops was better than theoretical predictions by maintaining lock across a wide range of loop gains and SNRs. However, when the loops were combined, the loops did not perform as predicted by theory. All simulations display phenomena which was not present in the theoretical predictions.

AFIT Designator

AFIT-GE-ENG-93D-13

DTIC Accession Number

ADA274037

Comments

The author's Vita page is omitted.

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