Date of Award
3-6-2007
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering
Department
Department of Electrical and Computer Engineering
First Advisor
Rusty O. Baldwin, PhD
Abstract
The contribution of this research is three-fold. The first is a method of converting the area occupied by a circuit implemented on a Field Programmable Gate Array (FPGA) to an equivalent as a measure of total gate count. This allows direct comparison between two FPGA implementations independent of the manufacturer or chip family. The second contribution improves the performance of the Advanced Encryption Standard (AES) on an 8-bit computing platform. This research develops an AES design that occupies less than three quarters of the area reported by the smallest design in current literature as well as significantly increases area efficiency. The third contribution of this research is an examination of how various designs for the critical AES SubBytes and MixColumns transformations interact and affect the overall performance of AES. The transformations responsible for the largest variance in performance are identified and the effect is measured in terms of throughput, area efficiency, and area occupied.
AFIT Designator
AFIT-GE-ENG-07-21
DTIC Accession Number
ADA469218
Recommended Citation
Silva, Ryan J., "Implementation and Optimization of the Advanced Encryption Standard Algorithm on an 8-Bit Field Programmable Gate Array Hardware Platform" (2007). Theses and Dissertations. 3142.
https://scholar.afit.edu/etd/3142