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Dynamic Model Validation Metric Based on Wavelet Thresholded Signals

Document Type

Article

Publication Date

6-14-2017

Abstract

Excerpt: Modern computing systems are primarily designed for maximum performance, which inadvertently introduces vulnerabilities at the micro-architecture level. While cache side-channel analysis has received significant attention, other Central Processing Units (CPUs) components like the Translation Lookaside Buffer (TLB) can also be exploited to leak sensitive information. This paper focuses on the TLB, a micro-architecture component that is vulnerable to side-channel attacks.

Comments

Copyright © 2017 by ASME.

This article is accessible to subscribers via the DOI link on this page.

[*] Author Andrew Atkinson was an AFIT PhD candidate at the time of this publication.

Source Publication

Journal of Verification, Validation and Uncertainty Quantification

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