Date of Award


Document Type


Degree Name

Doctor of Philosophy (PhD)


Department of Electrical and Computer Engineering

First Advisor

Mark A. Mehalic, PhD


This dissertation presents the development of a fast, accurate, timing simulation capability based on VHSIC Hardware Description Language VHDL without the use of back annotation of timing delay information. This VHDL-based timing simulator is intended for use with radiation-hardened microelectronics in simulating timing of circuit operation in pre-radiation, post-radiation 1 MradSi total dose, and ionizing dose radiation environments. Development of the timing models are presented. The implementation of the timing models are incorporated into a VHDL library composed of basic logic gates and flip-flops. Simulations of complex circuits were run in SPICE and VHDL to assess the timing accuracy and simulation run time of the VHDL-based timing simulator versus SPICE. Results of the simulations are presented. Final evaluation of the simulator included testing of a microprocessor control unit. In all cases, the VHDL-based simulation ran over two orders of magnitude faster than the equivalent SPICE simulation. In the pre- and post-radiation environment, accuracy estimates are usually within five percent and never exceed 12 percent. Worst-case timing estimate errors increase above 15 percent for dose rates above 1.Ox1Oexp 11 radsSi per second. This VHDL-based timing simulator represents an improvement over SPICE in the ability to quickly simulate complex circuits.

AFIT Designator


DTIC Accession Number