Date of Award
3-2006
Document Type
Thesis
Degree Name
Master of Science
Department
Department of Electrical and Computer Engineering
First Advisor
Rusty O. Baldwin, PhD
Abstract
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicate that there is no consistently better replacement method, regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is no preferred replacement method that will result in the lowest reconfiguration time.
AFIT Designator
AFIT-GE-ENG-06-26
DTIC Accession Number
ADA446930
Recommended Citation
Ives, Jason L., "Evaluation of a Field Programmable Gate Array Circuit Reconfiguration System" (2006). Theses and Dissertations. 3488.
https://scholar.afit.edu/etd/3488
Comments
Author vitae page not included.