A Comprehensive Security Analysis of and an Implementation Framework for Embedded Software Attestation Methods Leveraging FPGA-Based System-On-A-Chip Architectures

Patrick A. Reber


As embedded devices continue to proliferate, the safety and security of critical applications increasingly relies on trust in the running firmware. Malicious actors who compromise these devices may alter this code to accomplish their objectives while remaining undetected. Integrity checks of this code alerts users to changes which indicate a potential attack. This is commonly referred to as software attestation, and utilizes a challenge-response protocol that allows a trusted verifier to integrity check the memory of an untrusted device. This research assesses the potential for utilizing FPGA System-on-a-Chip (SoC) architectures for software attestation and analyzes the resulting security. A framework is proposed to leverage the SoC capabilities to quickly and easily perform software attestation with minimal runtime impact. The SoC hardware acts as a trusted local entity which aids in verification of the firmware run by the processor, while the incorporation of the SoC requires little processor software or configuration changes. This allows designs which previously utilized solely microcontrollers to easily port to this architecture for increased software security. This framework is constructed with an example algorithm and confirmed to detect attacks. The resulting degradation in processor speed is examined, as well as the potential attestation speed. Processor degradation ranges from 0.5 to 42 percent and read speed ranges from 0.06 to 3.2GB/s. Multiple additional alternatives are implemented and analyzed, which increase security at the cost of speed and simplicity. Various potential options are characterized in a novel attestation taxonomy extension for comparison.