Abstract
A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded microprocessor having access to the configuration memory, static modules, at least one relocatable module, and at least one spare module. The relocatable module being relocatable from a first target area to a second target area. The relocatable module being relocatable by manipulating a partial bitstream with the embedded microprocessor. The microprocessor calculating a plurality of bitstream changes, to relocate the at least one relocatable module using at least triple modular redundancy (TMR).
Document Type
Patent
Status
Issued
Issue Date
3-15-2011
Patent Number
US 7906984 B1 [7,906,984]
CPC Classification
H03K19/17732
Application number
12/393288
Assignees
Government of the United States, as represented by the Secretary of the Air Force, Wright-Patterson AFB, OH (US)
Filing Date
2-26-2009
Recommended Citation
Montminy, David P., Rusty O. Baldwin, and Paul D. Williams. Relocatable Field Programmable Gate Array Bitstreams for Fault Tolerance. United States Patent 7906984 (B1), issued 15 March 2011. https://scholar.afit.edu/patents/40