Date of Award

12-1992

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering

Department

Department of Electrical and Computer Engineering

First Advisor

Mark A. Mehalic, PhD

Abstract

Since 1985, the Air Force Institute of Technology has pursued a project to develop a 4080-point Discrete Fourier Transform processor using the Winograd Fourier Transform Algorithm (WFTA) and Good-Thomas Prime Factoring Algorithm (PFA). In the first attempt to build a working system, this research effort designed and constructed, in part, a modified single processor architecture in order to demonstrate the proof of concept of the WFTA system design. This prototype architecture is simpler in implementation but uses the same principles and procedures as those of the 4080-point WFTA design. The design developed in this thesis was validated using the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) to simulate its operation. A partial construction of the design was built and tested verifying the VHDL results.

AFIT Designator

AFIT-GCE-ENG-92D-05

DTIC Accession Number

ADA258919

Comments

The author's vita page is omitted.

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