Date of Award

12-1993

Document Type

Thesis

Degree Name

Master of Science

Department

Department of Electrical and Computer Engineering

First Advisor

Tom S. Wailes, PhD

Abstract

Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts of overloading. Results show that it is possible to maintain processor efficiency while reducing demand for channel availability.

AFIT Designator

AFIT-GCS-ENG-93D-1

DTIC Accession Number

ADA274127

Comments

The author's Vita page is omitted.

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