Partitioning Structural VHDL Circuits for Parallel Execution on Hypercubes

Author

Kevin L. Kapp

Date of Award

12-1993

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering

Department

Department of Electrical and Computer Engineering

Abstract

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural circuits ranging from one thousand to over four thousand behaviors are simulated. The deliberate partitions consistently provided superior speedup to a random distribution of the circuit behaviors.

AFIT Designator

AFIT-GCE-ENG-93D-07

DTIC Accession Number

ADA274390

Comments

The author's Vita page is omitted.

Recommended Citation

Kapp, Kevin L., "Partitioning Structural VHDL Circuits for Parallel Execution on Hypercubes" (1993). Theses and Dissertations. 6654.
https://scholar.afit.edu/etd/6654